Designing an integrated circuit (IC) or a system usually requires verification and/or debugging to ensure design correctness. One common practice may be based on hardware assisted verification (HAV) which provides visibility for a logic module by cloning the module and piping inputs to the module through a FIFO (First In First Out) delay buffer. U.S. Pat. No. 7,213,216 describes examples of such a practice. Simulation of test cases for the logic module can be performed on the cloned logic module using the buffered inputs. However, if a module contains multiple clocks (or in multiple clock domains), HAV may require all inputs to each clock domain to be buffered in a separate FIFO. As a result, additional hardware and complex software are required to synchronize simulation operations in each clock domain.
Furthermore, an FIFO implemented in an on-chip RAM (Random Access Memory) may be limited by the availability of unused memory space. To increase the amount of buffering in an FIFO, an off-chip memory, such as DDR2 (Double Data Rate 2) or SDRAM (Synchronous Dynamic RAM), may be employed. However, board real estate and/or pin limitations may prohibit implementing an FIFO using a single physical memory for each clock domain. Thus, multiple FIFOs' for different clock domains may be required to be built from a single physical memory.
Nevertheless, an off-chip memory may be limited by fixed data widths. In addition, separate address space for each FIFO may have severe bandwidth limitations caused by, for example, significant overhead in memory context switching.
Therefore, traditional data buffer for hardware assisted design verification does not provide an efficient and scalable solution. Furthermore, background information with respect to logic design or verification can be found in the following U.S. Pat. Nos. 5,036,473; 5,452,231; 5,596,742; 5,661,662; 5,761,484; 5,812,414; and 6,581,191.